In the past two decades, the market for wireless communication systems has shown unprecedented growth. In addition to the widespread proliferation of mobile phone services, wireless local area networks (WLANs) operating according to wireless standards such as IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and IEEE 802.16 are becoming more common. As the popularity of wireless systems increases, so does the demand for improved performance in the wireless transceivers supporting such systems.
One of the components in a wireless transceiver that can affect performance, particularly battery life and talk time, is the power amplifier. In general, power amplifiers for mobile transceivers can be divided into two groups: linear and saturated (non-linear). Generally speaking, a power amplifier operating in linear mode (referred to as a linear power amplifier) produces an output waveform having amplitudes that are directly proportional to the input waveform. Typically, the gain of this class of power amplifier remains fixed during operation and the output power is varied by varying the amplitude of the input waveform. For instance, a linear power amplifier may be preceded by a variable-gain amplifier (VGA). Linear amplification is typically used in transceivers to support signal processing methods such as Code Division Multiple Access (CDMA), Wide-band CDMA (W-CDMA), and Enhanced Data GSM Environment (EDGE) processing.
Power amplifiers operating in non-linear (saturated) mode (referred to as saturated power amplifiers) do not produce output waveforms that are directly proportional to the input waveforms. Instead, the output stage is driven on and off between a saturated state and an off state. Thus, a saturated power amplifier effectively operates as a switch and can be much more efficient than a linear amplifier. The output power in a saturated power amplifier generally varies with the supply voltage. Accordingly, for this class of power amplifier, the input power is typically fixed and either the supply voltage or the transistor bias voltages are varied to control gain, and thus the output power. Saturated power amplifiers are typically used in transceivers to support signal processing methods such as Group Speciale Mobile (GSM).
Because of the mobile nature of many wireless devices, the power amplification required for proper transmission is not necessarily constant. The power required for proper transmission is typically dependent on factors such as the distance of the handset to the corresponding base station or local terrain, and thus varies as the handset is transported from location to location. Consider, for example, a typical CDMA and GSM handset used in a cellular telephone network. Typical CDMA handsets are desirably capable of producing output powers of up to about +28 dBm, and typical GSM handsets are desirably capable of producing outputs power of up to about +34.5 dBm. The average output power that is necessary for such handsets, however, is far less than this maximum, and is generally closer to 0 dBm.
Further, GSM power amplifier modules are typically implemented with a controller (for example, a CMOS controller) used to modulate either the supply voltage or the base bias voltages in order to vary the gain of the amplifiers. A typical CMOS controller reduces excess voltage by dissipating it resistively. Consequently, lower-power operation can be very inefficient. For example, a typical saturated power amplifier with an efficiency of 55% at maximum output power is only about 24% efficient when the output power is reduced by 6 dB. Efficient operation at multiple power levels down to 0 dBm is therefore desirable for both linear and saturated amplifier applications, particularly for battery operated, mobile devices.
Conventional methods of implementing multi-power-mode amplifier functionality have traditionally involved complex switching arrangements. For example, U.S. Pat. No. 6,603,359 describes a multiple power mode power amplifier having a bypass circuit with a first bypass delay line having a line length of a quarter wavelength and a second bypass delay line having a line length of a quarter wavelength. The described bypass circuit further includes a switch circuit having three on-off contact switches. In particular, the switch circuit has a first on-off contact interposed between the bypass delay lines, a second on-off contact interposed between a grounding line and the connection between one side of the first contact and the first bypass delay line, and a third on-off contact interposed between a grounding line and the connection between another side of the first contact and the second delay line. When the first on-off contact is opened, the second and third contacts are closed, and when the first on-off contact is closed, the second and third contacts are opened. This complex switching arrangement completely isolates the bypass delay lines from one another during high-power operation by breaking the signal path through the switching circuit. The switch circuit and corresponding control circuitry, however, require significant amounts of hardware to implement this functionality. Moreover, the lengths of the bypass delay lines in the described design also require significant amounts of area in the overall design. Accordingly, the overall area required to implement the described bypass circuit is undesirably large, especially in view of today's demand for smaller power amplifier sizes. Further, in low-power operation, the switch circuit continuously draws a current in order to close the first on-off contact. Consequently, the switch circuit will exhibit undesirable power dissipation in low-power operation.
International Publication No. WO 03/065598 A1 describes a power amplifier having a variable gain amplifier, a first impedance matching unit, a second impedance matching unit, a power stage, a power stage output matching unit, an impedance transformer, and a switch. The switch in the described power amplifier is connected in parallel to the power stage to bypass the power stage according to the mode determined by the output power level. In high output power mode, the switch is closed and the first impedance matching unit and the second impedance matching unit are interoperated to constitute an interstage matching circuit. Thus, in the high output power mode, the second impedance matching unit and the path to ground created by closure of the switch are used as part of the interstage impedance match. The impedance and phase shift through the second impedance matching unit are thus constrained by matching requirements at the node where the bypass path begins.
Other multi-mode power amplifiers use bypass paths that exclude switches or other active elements of variable impedance or resistance altogether. For example, U.S. Pat. No. 6,900,692 and U.S. Patent Application Publication No. 2005/0083117 describe a multiple power mode power amplifier that does not use any switches and that is free from external control circuits provided to control the switches. The described amplifier has a driver for amplifying input power, a power stage for receiving power amplified by the driver through a first impedance matching unit connected to the driver and through a second impedance matching unit connected to the first impedance matching unit, and an applied voltage control circuit connected to the power stage for controlling applied voltages corresponding to a low-power mode and a high-power mode. The described amplifier further has an impedance transformer on a bypass arm for receiving power amplified by the driver through the first impedance matching unit and transferring the power to a fourth impedance matching unit. The described design also has a third impedance matching unit connected in series to the power stage for transferring power amplified by the power stage to the fourth impedance matching unit. The described amplifier requires a compromise in insertion losses between the high- and low-power modes. Consequently, in high-power mode, the described amplifier operates with reduced efficiency. Further, because of the inherent insertion losses in the design, higher amplifier gain (and thus more power) is required in both modes. Moreover, because the bypass arm is not highly isolated from the amplified path during high-power operation, the amplifier can be unstable due to signal feedback through the bypass arm. In fact, because phase shift changes with frequency, in high-power mode the undesired energy coupled through the bypass arm can also result in amplitude and phase distortions to the desired signal. Still further, because the bypass arm produces a frequency dependent load on the output, it is difficult to achieve desirable harmonic performance in implementations of the design.
Accordingly, there exists a need for improved amplifiers that are compact and that can operate with enhanced efficiency in multiple power modes, thereby providing the necessary peak power in one mode and efficient, low-power operation in another.